(1) Field of the Invention
This invention relates to an integrated circuit semiconductor device, and more particularly to a method for making improved deep trench capacitors for dynamic random access memory (DRAM) devices. The method uses a thicker pad silicon nitride (Si3N4) layer with a chemical-vapor-deposited glass layer as a hard mask for etching the deep trenches. This avoids overetching and damaging (faceting) the hard mask at the extreme edge of the wafer when the deep trenches are etched in the wafer. At a later processing step after completing the trench capacitors, the pad silicon nitride layer is used as a polish-back stop layer for making shallow trench isolation (STI). Due to the inherent properties of the chemical-mechanical polishing (CMP), the polish-back stop layer has reduced thickness at the center of the wafer (substrate) and is thicker at the wafer edge. To further improve process yield after CMP, the invention uses an additional patterned mask layer to protect the wafer center while exposing the silicon nitride stop layer at the wafer edge. The thicker portion of the pad Si3N4 layer is partially removed at the water edge to form a more uniform pad Si3N4.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are used for storing digital information on arrays of memory cells in the form of charge stored on capacitors. Each memory cell consists of a single access transistor and a single storage capacitor. The storage capacitors are formed either by etching deep trenches in the substrate in each cell area, commonly referred to as trench capacitors, or are formed over the access transistors in the cell areas by depositing and patterning conducting layers over the access transistors, and are commonly referred to as stacked capacitors. The capacitors make electrical contact to one of the two source/drain areas (node contacts) of each FET (access transistor), while bit lines make electrical contact to the other source/drain area of each FET. Read/write circuits, on the periphery of the DRAM chip, are used to store binary data by charging or discharging the storage capacitor via the bit lines, and the binary data is read (or sensed) by peripheral sense amplifiers, also via the bit lines. However, each capacitor must lie within an area about the size of the cell area in order to accommodate all the capacitors in the large array of cells used on the DRAM device.
As the number of memory cells increases on the DRAM chip and the cell areas decreases, it becomes increasingly difficult to fabricate the storage capacitors with reasonable surface area for maintaining sufficient capacitance (charge). For example, after the year 2000 the number of memory cells on a DRAM chip is expected to exceed several gigabits. Further, as the cell area decreases, the available area for the storage capacitor in each cell also decreases. This makes it difficult to maintain sufficient capacitance for storing charge to provide the necessary signal-to-noise ratios.
One method used in the semiconductor industry to overcome the above problems is to form DRAM devices with stacked capacitors or trench capacitors. However, the stacked capacitors, which are built on the chip surface, result in rough topography which makes subsequent processing difficult and requires leveling and planarizing techniques that can be expensive.
An alternative method for making an array of DRAM cells is by forming deep trench capacitors in the silicon substrate. The surface therefore remains essentially planar and available for wiring for the DRAM circuit. Also, by forming the storage capacitors in a trench etched in the silicon substrate, it is possible to leave the substrate surface free for the bit lines, thereby providing adequate separation between bit line and storage capacitor. This also allows memory cells to be built with smaller surface areas for future high-density DRAM arrays.
However, as the diameter of the trench decreases to sub-quarter-micrometer widths, it becomes necessary to significantly increase the trench depth. For example, for future gigabit DRAMs the aspect ratio (depth/width) of the trench can be greater than 35. Unfortunately, etching these narrow deep trenches in a silicon substrate can be difficult to achieve and can result in excessive erosion of the hard mask and lead to damage of the substrate surface. This problem is particularly exacerbated at the edge of the substrate (wafer), and the problem becomes more severe as the substrate diameter increases. To better appreciate this problem, FIGS. 1 and 2 show schematic cross-sectional views replicating SEM cross-sectional views for two adjacent trenches of the multitude of trenches formed. FIG. 1 shows a cross section of two adjacent trenches 2 formed in the substrate 10 away from the edge of the substrate, and FIG. 2 shows a cross section of two adjacent trenches 2 formed at the edge of the substrate. Typically the trenches are made by forming a thin stress-release silicon oxide layer (not shown), and depositing a pad Si3N4 layer 12 and a chemical-vapor-deposited silicon oxide layer 14 to form a hard-mask layer. The hard-mask layer (layers 12 and 14) is then patterned using conventional photolithographic techniques and plasma etching to etch a multitude of openings for deep trenches. After stripping the photoresist, the hard mask is used to selectively etch deep trenches 2 in the substrate 10, two of which are shown in FIG. 1.
Although the Si3N4 layer 12 is faceted at the point S, the trenches 2 in the silicon substrate 10 have essentially vertical sidewalls, and the trench openings replicate the hard-mask openings. However, during typical processing to deposit the hard-mask layer, the Si3N4 is thinner at the edge of the substrate, and the plasma etching to form the trenches in the substrate generally etches faster at the substrate edge. This results in excessive faceting that damages the substrate at the edge and distorts the trench profile 2, as shown at points S in FIG. 2. In more severe cases of overetching, the etching of the array of closely spaced trenches can result in a series of silicon needle-like structures. In both cases, the overetch reduces the usable surface area on the substrate, thereby reducing product yield.
Another problem occurs later in the trench capacitor process in which the chemical-mechanical polishing (CMP) to form the shallow trench isolation results in non-uniform polish-back of the shallow trench film material and also results in non-uniform etching of the underlying pad Si3N4 layer 12. The graph in FIG. 14 show the thickness profile of the pad Si3N4 layer 12 as a function of distance from the center of the wafer to the edge. The y axis shows the Si3N4 thickness, and the x axis is the distance from the center of a 200-millimeter diameter wafer. As can be seen the thickness of the Si3N4 increases significantly due to the polishing loading effect as one approaches the edge of the wafer. The two curves in the graph (FIG. 14) represent the variation in the Si3N4 thickness in Angstroms. Curve A shows the results for a new polishing pad, and curve B shows the results for the conventional process using a polishing pad after several passes. The results of the polishing show unacceptable (increased) variations in thickness as one approaches the edge of the wafer. Therefore, it is strongly desirable to improve the uniformity as indicated by the curve C in FIG. 14.
Several methods of making deep-trench capacitors are described in the literature. For example, Golden et al. in U.S. Pat. No. 5,618,751 teach a method for making a deep trench using a photoresist fill and recess to simplify the process and improve repeatable capacitor uniformity from wafer to wafer. In U.S. Pat. No. 6,071,823 to Hung et al. a method is described for making a bottle-shaped etched deep trench for increased capacitance. Yoshida in U.S. Pat. No. 5,885,863 teaches a method for making a simple contact to buried doped regions, such as the buried plate of a DRAM deep trench capacitor. Ohtsuki in U.S. Pat. No. 5,629,226 teaches a method for making deep trench capacitors having increased capacitance by widening the bottom portion of the trench while simultaneously achieving high density integration. However, none of the references addresses overetching deep trenches at the edge of the wafer that causes excessive faceting of the deep trenches. Also, none of the references addresses the non-nonuniformity in the pad Si3N4 thickness across the wafer that results from CMP, as described above with respect to FIG. 14.
There is still a strong need in the semiconductor industry to further improve upon fabricating deep trench capacitors for DRAM cells with increased reliability that improves process yield, especially at the edge of substrate.
Accordingly, a principal object of this invention is to provide an array of DRAM chip areas, each chip area having an array of sub-micrometer-wide deep trench capacitors with reduced trench overetching at the extreme edge of the substrate (wafer) to reduce hard-mask faceting and to increase product yield.
Another object of this invention is to reduce faceting and damage at the substrate edge by using a thicker silicon nitride/borosilicate glass hard mask to reduce overetching of the hard mask when etching deep trenches.
A further object of this invention is to improve the uniformity of the pad Si3N4 layer by reducing the thickness of the pad layer at the edge of the wafer resulting from CMP. This is achieved using an additional novel blanket photoresist mask layer over the center of the wafer and exposing the pad Si3N4 (polish-stop) layer at the wafer edge. The exposed polish-stop layer is then partially etched to provide a more uniform pad Si3N4 (etch-stop layer) across the wafer.
In accordance with the objectives of the present invention, a method is described for making an array of trench capacitors in which overetching at the wafer edge is minimized by using a thick Si3N4 pad layer, and at a later step a novel photoresist mask is used with a plasma etch to optimize the pad Si3N4 thickness at the wafer edge and to improve the uniformity across the wafer.
The method for making an array of deep trench capacitors for DRAM devices up to and including shallow trench isolation is briefly described. The method consists of providing a semiconductor substrate, preferably a single-crystal silicon substrate. An etch-stop layer consisting of a pad Si3N4 layer and a first insulating layer is deposited to form a hard mask. The pad Si3N4 layer is deposited to a thickness sufficient to prevent overetching at the edge of the wafer, which can cause faceting and wafer damage when deep trenches for capacitors are etched. The first insulating layer is a borosilicate glass (BSG). Next a photoresist mask and plasma etching are used to etch an array of openings in the hard-mask layer to the substrate. The photoresist mask is removed and the hard-mask is now used as an etch mask to etch deep trenches in the substrate for capacitors. The trench capacitors are now formed by depositing an arsenic-doped glass (ASG) and etching back to leave portions of the ASG in the lower part of the trenches. The substrate is then annealed to diffuse arsenic into the substrate to form first capacitor electrodes. The remaining ASG is removed by stripping. A capacitor interelectrode dielectric layer is formed by depositing a thin Si3N4 layer and reoxidizing to form a silicon oxide/silicon nitride (ON) capacitor interelectrode dielectric layer on the sidewalls of the trenches. An N doped first polysilicon layer is deposited and recessed to fill the lower portion of the trenches. The exposed portions of the interelectrode dielectric layer on the upper sidewalls of the trenches is removed. A blanket collar SiO2 layer is deposited on the substrate, annealed, and etched back to form a collar on the -upper portion of the sidewalls in the trenches. An N doped second polysilicon layer is deposited and recessed to leave portions in the upper part of the trenches to form the trench capacitors. An N doped third polysilicon layer is deposited and etched back to form interconnecting polysilicon straps to connect the trench capacitors to the substrate where semiconductor devices will be formed. Shallow trench openings are etched in the substrate over and between pairs of trench capacitors in the deep trenches. Shallow trench openings are also etched on the substrate for forming isolation regions for other circuits, such as DRAM peripheral circuits and merged logic/memory circuits. A short rapid thermal oxidation step is performed to form a thin SiO2 on the exposed polysilicon surfaces. A relatively thin conformal insulating liner, preferably composed of Si3N4, is deposited. A second insulating layer is deposited sufficiently thick to fill the shallow trench openings. The second insulating layer is polished back to the pad Si3N4 layer to form the shallow trench isolation. A key feature of this invention is to use a second mask layer composed of organic photoresist, and the mask is patterned to leave blanket portions of the third insulating layer over the center of the wafer while exposing the underlying pad Si3N4 layer at the wafer edge. The pad Si3N4 layer at the wafer edge is then partially etched to improve the Si3N4 uniformity across the wafer, and the second mask is removed in a plasma asher. This completes the array of deep trench capacitors, up to and including the shallow trench isolation, with reduced faceting at the wafer edge and more uniform Si3N4 thickness, thereby improving process yields.